Phase-looked loops, delay-locked loops, and switching regulators are vitally important devices. Phase-looked loops, delay-locked loops, and switching regulators are analog and mixed signal building blocks used extensively in communication, networks, digital systems, consumer electronics, computers, and any other fields that require frequency synthesizing and high efficient voltage regulating functions.
The phase-looked loop is a very versatile building block suitable for a variety of frequency synthesis, clock recovery, and synchronization applications. Prior Art FIG. 1 illustrates a basic architecture of a conventional phase-locked loop. The conventional phase-locked loop 100 typically consists of a phase-frequency detector, a charge-pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider in a loop. However, to understand phase-locked loops, phase-locked loops without any frequency dividers in a loop will be considered here. The phase-frequency detector is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector. Therefore, change in the low-pass filter's output voltage is used to drive the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.
In the conventional phase-locked loop of Prior Art FIG. 1, lock-in time is defined as the time that is required to attain lock from an initial loop condition. Assuming that the phase-locked loop bandwidth is fixed, the lock-in time is proportional to the initial difference frequency between the initial input signal frequency and the voltage-controlled oscillator's frequency as follows:
            (                        ω          in                -                  ω          osc                    )        2        ω    0    3  where ωin is the input signal frequency, ωosc is the voltage-controlled oscillator's frequency, and ω0 is the loop bandwidth. It should be noted that a loop bandwidth must be wide enough to obtain a fast lock-in time, unless the narrow bandwidth is inevitable to minimize output phase jitter due to external noise. If the loop bandwidth of a phase-locked loop is very narrow, the lock-in time is very slow. Modern communication systems require a fast lock-time time even though the loop bandwidth is narrow. However, the conventional phase-locked loops including Prior Art FIG. 1 have suffered from slow locking. Time and power are unnecessarily consumed until the phase-locked loops are in lock. To overcome the drawbacks, a conventional fast-locking phase-locked loop of Prior Art FIG. 2 is illustrated. The conventional fast-locking phase-locked loop consists of a digital phase-frequency detector including a 6-bit counter, a proportional-integral controller, a 10-bit digital-to-analog converter, and a voltage-controlled oscillator. Unfortunately, the conventional fast-locking phase-locked loop is costly, complicated, and inefficient in an integrated circuit (IC) because additional blocks such as the proportional-integral controller and the 10-bit digital-to-analog converter take much more chip area and consume much more power. Since there are much more functional blocks integrated on the same chip, the chip area of the conventional fast-locking phase-locked loop 200 is about three times as large as that of the conventional phase-locked loop 100. In addition, complicated additional functional blocks in a loop make the stability analysis very difficult. The complexity increases the number of blocks that need to be designed and verified. Thus, the conventional fast-locking phase-locked loop of Prior Art FIG. 2 might improve the lock-in time, but definitely results in the following penalties: bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. Therefore, the conventional fast-locking phase-locked loop 200 can not be implemented in an integrated circuit (IC). In addition to slow lock-in time problem, there have been serious harmonic locking problems when a multiplier is used for the phase detector.
Thus, what is desperately needed is a phase-locked loop integrated circuit that can attain a fast lock-in time and solve serious harmonic locking problems with an improvement in productivity, cost, chip area, power consumption, and design time. The present invention satisfies these needs by providing zero idle time Z-state circuits utilizing a small number of transistors.
Delay-looked loops are typically employed for the purpose of synchronization. Prior Art FIG. 3 illustrates a basic architecture of a conventional delay-locked loop. A conventional delay-locked loop 300 typically consists of a phase detector, a charge-pump, a loop filter, and a voltage-controlled delay line. In delay-locked loops, the phase detector is a block that has an output voltage with an average value proportional to the phase difference between the input signal clock and the output clock at the end of delay line. The charge-pump either injects the charge into the loop filter or subtracts the charge from the loop filter, depending on the outputs of the phase detector. Therefore, change in the loop filter's output voltage will affect the delay time of the voltage-controlled delay line. If delay different from integer multiples of clock period is detected, the closed delay-locked loop will automatically correct it by changing the delay time of the voltage-controlled delay line. However, conventional delay locked-loops have suffered from harmonic locking over wide operating range or failing to lock. To overcome the drawbacks, a conventional fast-locking delay-locked loop of Prior Art FIG. 4 is illustrated. The conventional fast-locking delay-locked loop 400 basically consists of an analog phase detector, a charge-pump, a loop filter, a voltage-controlled delay lines, a digital phase detector, a 2-bit successive-approximation register (SAR), and a DCDL. Unfortunately, the conventional fast-locking delay-locked loop is costly, complicated, and inefficient in an integrated circuit (IC) because additional blocks such as the DCDL and 2-bit successive-approximation register (SAR) take much more chip area and consume much more power. Since there are much more functional blocks integrated on the same chip, the chip area of the conventional fast-locking delay-locked loop 400 is about 2.6 times as large as that of the conventional delay-locked loop 300. The complexity increases the number of blocks that need to be designed and verified. Thus, the conventional fast-locking delay-locked loop of Prior Art FIG. 4 might improve the lock-in time, but certainly results in the following penalties: bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. Thus, the conventional fast-locking delay-locked loop 400 can not be implemented in an integrated circuit (IC). In addition to slow lock-in time problem, there have been serious lock failure problems.
Thus, what is desperately needed is a delay-locked loop integrated circuit that can attain a fast lock-in time and solve lock failure problems with an improvement in productivity, cost, chip area, power consumption, and design time. At the same time, what is desperately needed is to add one circuit that enables both phase-locked loops and delay-locked loops to achieve fast lock and to eliminate lock failure and harmonic locking problems. The present invention satisfies these needs by providing zero idle time Z-state circuits utilizing a small number of transistors, too.
Switching regulators (DC-TO-DC converters) are typically used for high efficient power supply system. Switching regulators can provide output voltages which can be less than, greater than, or of opposite polarity to the input voltage. Prior Art FIG. 5 illustrates a basic architecture of a conventional switching regulator 500. The conventional switching regulator basically consists of an oscillator, a reference circuit, an error amplifier, a modulator including a comparator, resistors, and a control logic circuit. Control technique of switching regulators has typically used two modulators: a pulse-width modulator and a pulse-frequency modulator. For pulse-width modulator, the output dc level is sensed through the feedback loop including two resistors. An error amplifier compares this sampled output voltage and the reference voltage. The output of the error amplifier is compared against a periodic ramp generated by the saw tooth oscillator. The pulse-width modulator output passes through the control logic to the high voltage power switch. The feedback system regulates the current transfer to maintain a constant voltage within the load limits. In other words, it insures that the output voltage comes into regulation. Unfortunately, the conventional switching regulator 500 is inefficient in an integrated circuit (IC). The reason why is that it takes a long time until the regulated output reaches the equilibrium after the power supply or the power system starts. Thus, power and time are wasted until the output voltage comes into regulation. In addition, the slow start-up increases design simulation time.
In summary, unfortunately the conventional phase-locked loop 100 of Prior Art FIG. 1, the conventional fast-locking phase-locked loop 200 of Prior Art FIG. 2, the conventional delay-locked loop 300 of Prior Art FIG. 3, the conventional fast-locking delay-locked loop 400 of Prior Art FIG. 4, and the conventional switching regulator 500 of Prior Art FIG. 5 are very inefficient and unreliable to implement in an integrated circuit. In addition, those integrated circuits 100, 200, 300, 400, and 500 have taken a long time to be simulated and verified before they are fabricated. Also, many other additional drawbacks are described as follows: First, the conventional phase-locked loops 100 and conventional delay-locked loop 300 have suffered from a very long time required to attain lock. Hence, time and power are unnecessarily consumed until the conventional phase-locked loop 100 and conventional delay-locked loop 300 are in lock. Second, the conventional phase-locked loop 100 has suffered from harmonic locking and the conventional delay-locked loop 300 has suffered from failing to lock. Especially harmonic locking is that the phase-locked loop locks to harmonics of the input signal when a multiplier is used for the phase detector. Third, the conventional switching regulator 500 has suffered from long time to require the output voltage to be regulated. Fourth, simulation time in designing these integrated circuits is absolutely proportional to time required the loops to lock and time to require the output voltage of the switching regulators to be regulated. Hence, this long simulation time adds additional cost to the integrated circuit (IC) and slows down design time to market. Fifth, the conventional locked loops and the conventional switching regulators do not have common analog building block to reduce the number of different blocks that need to be designed and verified. As a result, regularity and productivity can not be achieved. Sixth, the conventional fast-locking phase-locked loop 200 and conventional fast-locking delay-locked loop 400 might improve the lock-in time, but definitely results in bad productivity, higher cost, larger chip area, much more power consumption, and longer design time.
Thus, what is finally needed for a cost-effective circuit that can make a fast lock-in time for phase-locked loops and delay-locked loops, resolve harmonic locking for phase-locked loops, prevent delay-locked loops from failing to lock, minimize start-up time of switching regulators, reduce power and time consumption until loops are in lock or the output voltage of switching regulators comes into regulation, reduce significantly design time for better time-to-market, and improve productivity by reusing the same cost-effective circuit design for three applications such as phase-locked loops, delay-locked loops, and switching regulators. The present invention satisfies these needs by providing four embodiments utilizing a small number of transistors.